The present invention relates to the field of signal synchronizing and frequency synthesis circuits for sequence control of integrated circuit logic. More specifically, the present invention relates to a signal synchronizing and frequency synthesis circuit of the phase locked loop type.
Synchronization of a microprocessor system is accomplished through the use of one or more clock signals. Each component within the system uses a clock signal to synchronize the particular component""s internal sequential logic circuitry to that of the entire system in order to operate in accordance with the desired operating protocol standard. In high-speed systems, synchronization of clock signals with each of the clocked components must be maintained with high efficiency to eliminate or reduce system timing errors and delays which may result. A system utilized in maintaining the synchronization of microprocessor systems is the phase lock loop (PLL).
Signal synchronizing and frequency synthesis circuitry such as PLLs are used in synchronous microprocessor systems. In integrated circuit (IC) logic, PLLs are used in order to minimize timing delays and errors which may occur due to the delays. A PLL can be used to synchronize a plurality of signals to conform to a desired frequency signal. The synchronization of the plurality of signals allows a plurality of circuits within the same system to operate in accordance with a desired timing protocol.
Problems in synchronization may occur when various clock signals operating within the same system become misaligned in phase, i.e. skewed, while passing through intermediate circuitry having varying propagation delays. In a high-speed multiple chip computer system, it is desirable to maintain the phase difference between clock signals at various locations in the system to a specified minimum value. However, variations in propagation can be caused by variations in circuitry structure or tolerance associated with the system""s manufacturing process.
Additionally, synchronizing or timing problems may occur with respect to typical microprocessor systems that have an external clock signal and another clock signal which is internal to the microprocessor core. These two external and internal clock signals may sometimes become out of phase in relation to each other, as between the clock signal internal to the microprocessor core and inputs generated by a clock signal external to the microprocessor core.